1. Field of the Invention
The invention relates to a method for pulling a silicon single crystal, in which the single crystal is pulled at a certain speed in the vertical direction with respect to a silicon melt held in a crucible.
2. The Prior Art
This method named after its inventor Czochralski provides single crystals which are doped with a high content of oxygen originating from the quartz crucibles normally used. The high oxygen doping results in the formation of oxidation-induced stacking faults (OSF) in the single crystal. It has already been established that the spatial distribution with which OSFs occur in silicon wafers cut from single crystals is dependent substantially on the pulling speed during the pulling of the single crystal. According to a report in "Defect Control in Semiconductors" (M. Hasebe et al., Elsevier Science Publishers B. V., page 157 (1990)), OSFs occur in high density inside an annular region of silicon wafers if the single crystal was pulled at a pulling speed of 0.5 to 1.0 mm/min. The annular region, hereinafter referred to as the stacking-fault ring, is undesirable since OSFs are as a rule extremely troublesome in that region of the silicon wafer into which electronic components are to be integrated.
The stacking-fault ring is situated concentrically with respect to the circumference of the silicon wafer. Its radius is smaller or larger as a function of the speed with which the single crystal was pulled. If the pulling speed was just above the lower limit specified of 0.5 mm/min, the stacking-fault ring is situated closely around the wafer center. If the single crystal was pulled at a speed just below the upper limit specified of 1.0 mm/min, the stacking-fault ring is already situated close to the circumference line of the silicon wafer.
European Patent Application EP-503 816 A1 discloses that additional crystal defects occur inside the stacking-fault ring all the more often, the higher the speed was in pulling the single crystal. A high density of said crystal defects impairs, in particular, the breakdown strength of dielectric oxide films, which are created on a side face of the silicon wafer in order to produce large-scale integrated circuits.
It can be demonstrated (M. Hourai et al., Proceedings of Progress in Semiconductor Fabrication, Technical Conference at Semicon Europe 1993, Semicon Europe, Belgium (1993)) that the breakdown strength of oxide films, frequently referred to as gate oxide integrity (GOI), varies significantly in silicon wafers with a stacking-fault ring, depending on whether it is measured in a region inside or outside the stacking-fault ring. Thus, the GOI in a region outside the stacking-fault ring meets the high requirements which are imposed on the breakdown strength of a dielectric oxide film in the production of components. On the other hand, the GOI inside the stacking-fault ring is completely inadequate. In accord with the teaching of EP-503 816 A1, the GOI in silicon wafers of single crystals which have been pulled so rapidly that a stacking-fault ring can no longer be observed is inadequate in the entire region of the silicon wafer suitable for the integration of components.
To improve the GOI of silicon wafers originating from a single crystal which has been pulled at an economical speed of over 0.8 mm/min, the above-mentioned European patent specification proposes subjecting the silicon wafers to a temperature treatment in the range 1150.degree. C. to 1280.degree. C. For the same purpose, a certain thermal treatment of the single crystal during the pulling operation is recommended in European Patent Application EP-504 837 A2. Accordingly, the pulling conditions are to be adjusted and maintained so that at least a part of the growing single crystal whose temperature is above 1150.degree. C. is situated at a distance of more than 280 mm above the melt surface.
Both proposals pursue the aim of improving the GOI quality. The occurrence of the stacking-fault ring at high pulling speeds is not obviated by the prior art.